--
-- VHDL Architecture bit_rev_test_lib.test.arch
--
-- Created:
--          by - patli862.student (southfork-14.edu.isy.liu.se)
--          at - 14:00:39 10/14/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_arith.all;
use IEEE.numeric_std.all;


ENTITY test IS
port(
  count : buffer integer := 8;
  ut    : out     integer
  );
END ENTITY test;

--
ARCHITECTURE arch OF test IS
signal org : std_logic_vector(7 downto 0);
signal rev : std_logic_vector(7 downto 0);
BEGIN
  
org <= std_logic_vector(to_unsigned(count,8));
  
rev(0)<=org(7);
rev(1)<=org(6);
rev(2)<=org(5);
rev(3)<=org(4);
rev(4)<=org(3);
rev(5)<=org(2);
rev(6)<=org(1);
rev(7)<=org(0);
 
ut <= to_integer(unsigned(rev));
END ARCHITECTURE arch;

